/*
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Language: Verilog
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Author: Jon Evans <jon@craftyjon.com>
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Contributors: Boone Severson <boone.severson@gmail.com>
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Description: Verilog is a hardware description language used in electronic design automation to describe digital and mixed-signal systems. This highlighter supports Verilog and SystemVerilog through IEEE 1800-2012.
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Website: http://www.verilog.com
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*/
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function verilog(hljs) {
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const SV_KEYWORDS = {
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$pattern: /[\w\$]+/,
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keyword:
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'accept_on alias always always_comb always_ff always_latch and assert assign ' +
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'assume automatic before begin bind bins binsof bit break buf|0 bufif0 bufif1 ' +
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'byte case casex casez cell chandle checker class clocking cmos config const ' +
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'constraint context continue cover covergroup coverpoint cross deassign default ' +
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'defparam design disable dist do edge else end endcase endchecker endclass ' +
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'endclocking endconfig endfunction endgenerate endgroup endinterface endmodule ' +
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'endpackage endprimitive endprogram endproperty endspecify endsequence endtable ' +
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'endtask enum event eventually expect export extends extern final first_match for ' +
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'force foreach forever fork forkjoin function generate|5 genvar global highz0 highz1 ' +
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'if iff ifnone ignore_bins illegal_bins implements implies import incdir include ' +
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'initial inout input inside instance int integer interconnect interface intersect ' +
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'join join_any join_none large let liblist library local localparam logic longint ' +
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'macromodule matches medium modport module nand negedge nettype new nexttime nmos ' +
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'nor noshowcancelled not notif0 notif1 or output package packed parameter pmos ' +
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'posedge primitive priority program property protected pull0 pull1 pulldown pullup ' +
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'pulsestyle_ondetect pulsestyle_onevent pure rand randc randcase randsequence rcmos ' +
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'real realtime ref reg reject_on release repeat restrict return rnmos rpmos rtran ' +
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'rtranif0 rtranif1 s_always s_eventually s_nexttime s_until s_until_with scalared ' +
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'sequence shortint shortreal showcancelled signed small soft solve specify specparam ' +
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'static string strong strong0 strong1 struct super supply0 supply1 sync_accept_on ' +
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'sync_reject_on table tagged task this throughout time timeprecision timeunit tran ' +
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'tranif0 tranif1 tri tri0 tri1 triand trior trireg type typedef union unique unique0 ' +
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'unsigned until until_with untyped use uwire var vectored virtual void wait wait_order ' +
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'wand weak weak0 weak1 while wildcard wire with within wor xnor xor',
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literal:
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'null',
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built_in:
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'$finish $stop $exit $fatal $error $warning $info $realtime $time $printtimescale ' +
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'$bitstoreal $bitstoshortreal $itor $signed $cast $bits $stime $timeformat ' +
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'$realtobits $shortrealtobits $rtoi $unsigned $asserton $assertkill $assertpasson ' +
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'$assertfailon $assertnonvacuouson $assertoff $assertcontrol $assertpassoff ' +
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'$assertfailoff $assertvacuousoff $isunbounded $sampled $fell $changed $past_gclk ' +
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'$fell_gclk $changed_gclk $rising_gclk $steady_gclk $coverage_control ' +
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'$coverage_get $coverage_save $set_coverage_db_name $rose $stable $past ' +
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'$rose_gclk $stable_gclk $future_gclk $falling_gclk $changing_gclk $display ' +
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'$coverage_get_max $coverage_merge $get_coverage $load_coverage_db $typename ' +
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'$unpacked_dimensions $left $low $increment $clog2 $ln $log10 $exp $sqrt $pow ' +
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'$floor $ceil $sin $cos $tan $countbits $onehot $isunknown $fatal $warning ' +
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'$dimensions $right $high $size $asin $acos $atan $atan2 $hypot $sinh $cosh ' +
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'$tanh $asinh $acosh $atanh $countones $onehot0 $error $info $random ' +
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'$dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson ' +
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'$dist_t $dist_uniform $q_initialize $q_remove $q_exam $async$and$array ' +
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'$async$nand$array $async$or$array $async$nor$array $sync$and$array ' +
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'$sync$nand$array $sync$or$array $sync$nor$array $q_add $q_full $psprintf ' +
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'$async$and$plane $async$nand$plane $async$or$plane $async$nor$plane ' +
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'$sync$and$plane $sync$nand$plane $sync$or$plane $sync$nor$plane $system ' +
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'$display $displayb $displayh $displayo $strobe $strobeb $strobeh $strobeo ' +
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'$write $readmemb $readmemh $writememh $value$plusargs ' +
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'$dumpvars $dumpon $dumplimit $dumpports $dumpportson $dumpportslimit ' +
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'$writeb $writeh $writeo $monitor $monitorb $monitorh $monitoro $writememb ' +
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'$dumpfile $dumpoff $dumpall $dumpflush $dumpportsoff $dumpportsall ' +
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'$dumpportsflush $fclose $fdisplay $fdisplayb $fdisplayh $fdisplayo ' +
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'$fstrobe $fstrobeb $fstrobeh $fstrobeo $swrite $swriteb $swriteh ' +
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'$swriteo $fscanf $fread $fseek $fflush $feof $fopen $fwrite $fwriteb ' +
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'$fwriteh $fwriteo $fmonitor $fmonitorb $fmonitorh $fmonitoro $sformat ' +
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'$sformatf $fgetc $ungetc $fgets $sscanf $rewind $ftell $ferror'
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};
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return {
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name: 'Verilog',
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aliases: [
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'v',
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'sv',
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'svh'
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],
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case_insensitive: false,
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keywords: SV_KEYWORDS,
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contains: [
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hljs.C_BLOCK_COMMENT_MODE,
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hljs.C_LINE_COMMENT_MODE,
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hljs.QUOTE_STRING_MODE,
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{
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className: 'number',
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contains: [ hljs.BACKSLASH_ESCAPE ],
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variants: [
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{
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begin: '\\b((\\d+\'(b|h|o|d|B|H|O|D))[0-9xzXZa-fA-F_]+)'
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},
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{
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begin: '\\B((\'(b|h|o|d|B|H|O|D))[0-9xzXZa-fA-F_]+)'
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},
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{
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begin: '\\b([0-9_])+',
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relevance: 0
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}
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]
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},
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/* parameters to instances */
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{
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className: 'variable',
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variants: [
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{
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begin: '#\\((?!parameter).+\\)'
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},
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{
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begin: '\\.\\w+',
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relevance: 0
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}
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]
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},
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{
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className: 'meta',
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begin: '`',
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end: '$',
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keywords: {
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'meta-keyword':
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'define __FILE__ ' +
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'__LINE__ begin_keywords celldefine default_nettype define ' +
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'else elsif end_keywords endcelldefine endif ifdef ifndef ' +
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'include line nounconnected_drive pragma resetall timescale ' +
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'unconnected_drive undef undefineall'
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},
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relevance: 0
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}
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]
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};
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}
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module.exports = verilog;
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